PXD20RM Datasheet, PDF (300/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Field
24–27
DT[0:3]
28–31
BR[0:3]
Table 10-5. DSPIx_CTARn Field Descriptions (continued)
Descriptions
Delay after Transfer Scaler. The DT field selects the Delay after Transfer Scaler. This field is only used
in Master Mode. The Delay after Transfer is the time between the negation of the PCS signal at the
end of a frame and the assertion of PCS at the beginning of the next frame. Table 10-10 lists the
scaler values. In the Continuous Serial Communications Clock operation the DT value is fixed to one
TSCK, except when the TSBC bit from DSPI_DSICR register is enabling the TSB configuration. The
Delay after Transfer is a multiple of the system clock period and it is computed according to the
following equation:
t_DT
=
-----¹-----  PDT  DT
f_SYS
Eqn. 10-3
Baud Rate Scaler. The BR field selects the scaler value for the baud rate. This field is only used in
Master Mode. The prescaled system clock is divided by the Baud Rate Scaler to generate the
frequency of the SCK. Table 10-11 lists the Baud Rate Scaler values.The baud rate is computed
according to the following equation:
SCK baud rate = -^f--^S---^Y----^S-  ¹-----⁺-----^D-----^B----^R--
PBR BR
Eqn. 10-4
Table 10-6. DSPI SCK Duty Cycle
DBR
0
1
1
1
1
1
1
1
1
CPHA
any
0
0
0
0
1
1
1
1
PBR
any
00
01
10
11
00
01
10
11
SCK Duty Cycle
50/50
50/50
33/66
40/60
43/57
50/50
66/33
60/40
57/43
FMSZ
0000
0001
0010
0011
0100
0101
0110
0111
Table 10-7. DSPI Transfer Frame Size
Framesize
Reserved
Reserved
Reserved
4
5
6
7
8
FMSZ
1000
1001
1010
1011
1100
1101
1110
1111
Framesize
9
10
11
12
13
14
15
16
10-14
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor