PXD20RM Datasheet, PDF (1493/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

31
SIU Base+ 0x0000
23
15
7
0
32-bit Port
15
SIU Base+
0x0002
7
0
SIU Base+
0x0003
8-bit Port
7
0
16-bit Port
7
0
SIU Base+
0x0002
8-bit Port
15
7
0
SIU Base+
0x0000
16-bit Port
7
0
SIU Base+
0x0001
8-bit Port
7
0
SIU Base+
0x0000
8-bit Port
Figure 43-21. Data Port example arrangement showing configuration for different port width accesses
This implementation requires that the registers are arranged in such a way as to support this range of port
widths without having to split reads or writes into multiple accesses.
The SIUL has separate data input (GPDIn_n, see Section 43.5.3.12, GPIO Pad Data Input Registers
(GPDI0_3–GPDI184)) and data output (GPDOn_n, see Section 43.5.3.11, GPIO Pad Data Output
Registers (GPDO0_3 - GPDO184)) registers for all pads, allowing the possibility of reading back an input
or output value of a pad directly. This supports the ability to validate what is present on the pad rather than
simply confirming the value that was written to the data register by accessing the data input registers.
Data output registers allow an output pad to be driven high or low (with the option of push-pull or open
drain drive). Input registers are read-only and reflect the respective pad value.
When the pad is configured to use one of its alternate functions, the data input value reflect the respective
value of the pad. If a write operation is performed to the data output register for a pad configured as an
alternate function (non GPIO), this write will not be reflected by the pad value until reconfigured to GPIO.
The allocation of what input function is connected to the pin is defined by the PSMI registers (PCRn, see
Section 43.5.3.8, Pad Configuration Registers (PCR0–PCR184)).
43.6.4 External interrupts
The SIUL supports 24 external interrupts, EIRQ0–EIRQ23. The mapping of these interrupts to external
pins is summarized in Table 43-1 and described in full detail in Chapter 3, Signal Description.
The SIUL supports three interrupt vectors to the interrupt controller. Each vector interrupt has eight
external interrupts combined together with the presence of flag generating an interrupt for that vector if
enabled. All of the external interrupt pads within a single group have equal priority.
Refer to Figure 43-22 for an overview of the External Interrupt implementation.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
43-27