PXD20RM Datasheet, PDF (1516/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

46.3.3.2 Bit Mapping Control (TCON_BMC)
Offset 0x0004
Access: User read/write
Power ₀
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Architecture
Conventional ₃₁
30
29
28
27
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24
23
22
21
20
19
18
17
16
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Power ₁₆
17
18
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20
21
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23
24
25
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30
31
Architecture
Conventional _{15 14}
13
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7
6
5
4
3
2
1
0
R0 0 0 0 0 0
W
CLK_POS
COLOR_ORDER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 46-3. TCON_BMC Register
Table 46-5. TCON_BMC Register Field Descriptions
Field
Description
CLK_POS
clock position selection, output pixel clock can be assigned to any data_out pins.
For RSDS mode, see Table 46-31 for detailed mapping relationship.
For TTL mode, see Table 46-32 for detailed mapping relationship.
COLOR_ORDER
Color component order configuration bits.
000: RGB
001: BRG
010: GBR
011: RBG
100: GRB
101: BGR
Other values:are reserved.for use
BIT_ORDER
0: MSB 7 down to LSB 0 for every color component
1: LSB 0 upto MSB 7, for every color component. (inverted order)
BIT_SWAP
0: No swap
1: Swap odd and even bits for every color component: bit 6 and 7, 4 and 5, 2 and 3, 0 and 1 are swapped.
This is needed for RSDS channel order inversion
46.3.3.3 TCON_COMP0 - TCON_COMP3
46-8
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor