PXD20RM Datasheet, PDF (240/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 8-33. Examples of typical PLL settings
Crystal
Frequency
(MHz)
PLL Output
Frequency
(MHz)
DRAM clock
Frequency
(MHz)
Register Values
IDF ODF NDIV
VCO
Frequency
(MHz)
10
30
60
80
125
60
0
2
48
480
120
0
1
48
480
160
1
0
64
320
250
0
0
50
500
8.5.6.2 Progressive clock switching
Progressive clock switching allows to switch system clock to PLL output clock stepping through different
division factors. This means that the current consumption gradually increases and so the voltage regulator
has a better response.
This feature can be enabled by programming the en_pll_sw bit in CR. Then, when the input pin pll_select
goes high, the output clock ck_pll_div will progressively increase its frequency as described in Table 8-34
and Figure 8-31.
Table 8-34. Progressive clock switching on pll_select rising edge
Number of PLL output clock cycles
ck_pll_frequency (PLL output clock frequency)
8
16
32
onward
(ck_pll_out frequency)/8
(ck_pll_out frequency)/4
(ck_pll_out frequency)/2
(ck_pll_out frequency)
ck_pll_out


ck_pll_div


Figure 8-31. Diagram of progressive clock switching
8.5.6.3 Normal Mode with frequency modulation
The FMPLL default mode is without frequency modulation enabled. When frequency modulation is
enabled, however, two parameters must be set to generate the desired level of modulation: the PERIOD,
and the STEP. The modulation waveform is always a triangle wave and its shape is not programmable.
FM modulation shall be activated in two steps:
8-44
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor