PXD20RM Datasheet, PDF (711/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

18.6.2 Register description
All control registers are 32 bits wide. This document illustrates the eMIOS200 with 24 Unified Channels
and 16-bit wide data registers.
18.6.2.1 eMIOS200 Module Configuration Register (MCR)
The MCR contains Global Control bits for the eMIOS200 block.
address: eMIOS200 base address +0x00
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R _{0 MDIS FRZ 0}
0 GPRE 0
0
0
0
0
0
0
0
0
0
W
N
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
GPRE
0
0
0
0
0
0
0
0
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Field
MDIS
FRZ
= Unimplemented or Reserved
Figure 18-4. eMIOS200 Module Configuration Register (MCR)
Table 18-7. MCR field descriptions
Description
Module Disable
Puts the eMIOS200 in low power mode. The MDIS bit is used to stop the clock of the block, except
the access to registers MCR, OUDR and UCDIS.
1 = Enter low power mode
0 = Clock is running
Freeze
Enable the eMIOS200 to freeze the registers of the Unified Channels when Debug Mode is requested
at MCU level. Each Unified Channel should have FREN bit set in order to enter freeze state. While in
Freeze state, the eMIOS200 continues to operate to allow the MCU access to the Unified Channels
registers. The Unified Channel will remain frozen until the FRZ bit is written to zero or the MCU exits
Debug mode or the Unified Channel FREN bit is cleared.
1 = Stops Unified Channels operation when in Debug mode and the FREN bit is set in the CCR[n]
register
0 = Exit freeze state
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
18-9