PXD20RM Datasheet, PDF (530/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

periods. The BP_H bit field defines the delay between the end of the HSYNC pulse and the start of the
data enable signal (and pixel data delivery), in pixel clock periods. The FP_H bit field defines the delay
between the end of the data enable signal (and pixel data delivery) and the next HSYNC pulse, in pixel
clock periods. FP_H and BP_H have minimum values of 1.
If the TFT LCD panel requires a vertical synchronizing signal (VSYNC), then this can be configured using
the fields in the VSYN_PARA register. VSYNC provides a pulse to give the panel notice that the next
frame of pixel data lines is about to start, and the panel defines delays before and after this pulse, in terms
of pixel clock periods. The PW_V bit field indicates the width of the VSYNC pulse in horizontal line
periods. The BP_V bit field defines the delay between the end of the VSYNC pulse and the start of the
next pixel data (data enable signal), in horizontal line periods. The FP_V bit field defines the delay
between the end of the last pixel data (data enable signal) and the next VSYNC pulse, in horizontal line
periods. FP_V and BP_V have minimum values of 1.
The polarity of all these signals, including the pixel data itself, may be inverted by using the control bits
in the SYN_POL register.
The refresh rate for the panel can be calculated using Equation 12-1 and Equation 12-2 below.
where:
RR
=
---------------------------------------------------------------------------^p--ⁱ-^x---^_--^c--^l-^k---------------------------------------------------------------------------
DELTA_X + FP_H + PW_H + BP_H  DELTA_Y + FP_V + PW_V + BP_V
pix_clk is the pixel clock
DELTA_X is the horizontal resolution (in pixels)
DELTA_Y is the vertical resolution (in pixels)
FP_H is the HSYNC front porch pulse width (in pixel clock cycles)
BP_H is the HSYNC back porch pulse width (in pixel clock cycles)
PW_H is the HSYNC active pulse width (in pixel clock cycles)
FP_V is the VSYNC front porch pulse width (in pixel clock cycles)
BP_V is the VSYNC back porch pulse width (in pixel clock cycles)
PW_V is the VSYNC active pulse width (in pixel clock cycles)
Eqn. 12-1
Pixel Clock = (DCULite Clock) / PRESCALE VALUE
where PRESCALE VALUE is an integer value that can range from 2–32.
Eqn. 12-2
12.4.3 DCULite mode selection and background color
Once the DCULite is configured for use with a particular TFT LCD panel, it can be enabled for use. There
are five modes to choose from, as shown in Table 12-56.
Table 12-56. List of DCULite operating modes
Mode
DCU_MODE[1:0] PDI_EN
Description
Off
00
X
DCULite disabled; the TFT LCD panel is not driven.
Color bar
11
X
DCULite displays a test pattern consisting of vertical bands of
programmable color.
12-68
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor