PXD20RM Datasheet, PDF (525/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 12-52. Soft Lock HSYNC/VSYNC PARA Register field descriptions (continued)
Field
SLB_HSYNC
SLB_VSYNC
Description
Soft Lock Bit for HSYNC Register. This bit cannot be cleared once set by software. Can only be
cleared by system reset.
1’b1: Associated protected register is locked for write access
1’b0: Associated protected register is not locked & writeable
Soft Lock Bit for VSYNC Register. This bit cannot be cleared once set by software. Can only be
cleared by system reset.
1’b1: Associated protected register is locked for write access
1’b0: Associated protected register is not locked & writeable
12.3.4.49 Soft Lock POL Register
Figure 12-59 represents the Soft Lock POL Register.
Offset: 0x314
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0
00000000000
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1
Figure 12-59. Soft Lock POL Register
Table 12-53. Soft Lock POL Register field descriptions
Field
WEN_POL
SLB_POL
Description
Write Enable for Soft Lock Bit SLB_POL
1’b1: Value is written to SLB
1’b0: SLB is not modified
Soft Lock Bit for SYN_POL Register. This bit cannot be cleared once set by software. Can only
be cleared by system reset.
1’b1: Associated protected register is locked for write access
1’b0: Associated protected register is not locked & writeable
12.3.4.50 Soft Lock L0_TRANSP Register
Figure 12-60 represents the Soft Lock L0_TRANSP register.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
12-63