PXD20RM Datasheet, PDF (714/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

address: eMIOS0 base address +0x08
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R₀
0
0
0
0
0
0
0 OU23 OU22 OU21 OU20 OU19 OU18 OU17 OU16
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{OU15 OU14 OU13 OU12 OU11 OU10 OU9 OU8 0}
0
0
0
0
0
0
0
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Field
OU[n]
= Unimplemented or Reserved
Figure 18-6. eMIOS200 Output Update Disable Register (OUDR)
Table 18-9. OUDR field descriptions
Description
Channel [n] Output Update Disable bit
When running MCB or an output mode, values are written to registers A2 and B2. OU[n] bits are used
to disable transfers from registers A2 to A1 and B2 to B1. Each bit controls one channel.
1 = Transfers disabled
0 = Transfer enabled. Depending on the operation mode, transfer may occur immediately or in the
next period. Unless stated otherwise, transfer occurs immediately.
18.6.2.4 eMIOS200 Disable Channel (UCDIS)
The two modules on this device, EMIOS0 and EMIOS1, have the same structure for this register as shown
in Figure 18-7.
18-12
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor