PXD20RM Datasheet, PDF (1002/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

27.10.17 Identifier filter enable register (IFER)
Offset: 0x40
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0
W
FACT¹
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 _{This field is writable only in Initialization mode (LINCR1[INIT] = 1).}
Figure 27-34. Identifier filter enable register (IFER)
Table 27-31. IFER field descriptions
Field
FACT
Description
Filter active
The software sets the bit FACT[x] to activate the filter x in identifier list mode.
In identifier mask mode bits FACT(2n + 1) have no effect on the corresponding filters as they act as
masks for the Identifiers 2n.
These bits can be set/cleared in Initialization mode only.
27.10.18 Identifier filter match index (IFMI)
Offset: 0x44
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R₀
0
0
0
0
0
0
0
0
0
0
IFMI
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 27-35. Identifier filter match index (IFMI)
27-46
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor