PXD20RM Datasheet, PDF (760/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 19-8. Flash ECC Attributes (FEAT) Field Descriptions (continued)
Name
Description
1-3
Size[0:2]
AMBA-AHB HSIZE[0:2]
0b000 = 8-bit AMBA-AHB access
0b001 = 16-bit AMBA-AHB access
0b010 = 32-bit AMBA-AHB access
0b1xx = Reserved
4-7
Protection[0:3]
AMBA-AHB HPROT[0:3]
Protection[3]: Cacheable 0 = Non-cacheable,1 = Cacheable
Protection[2]: Bufferable0 = Non-bufferable,1 = Bufferable
Protection[1]: Mode 0 = User mode, 1 = Supervisor mode
Protection[0]: Type 0 = I-Fetch, 1 = Data
19.4.2.9 Flash ECC Data Register (FEDR)
The FEDR is a 32-bit register for capturing the data associated with the last, properly-enabled ECC event
in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash
causes the address, attributes and data associated with the access to be loaded into the FEAR, FEMR,
FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be
asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 19-8 and Table 19-9 for the Flash ECC Data Register definition.
Register address: ECSM Base +0x5C
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
FEDR[0:15]
W
RESET: x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
FEDR[16:31]
W
RESET: x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
= Unimplemented
Figure 19-8. Flash ECC Data (FEDR) Register
Table 19-9. Flash ECC Data (FEDR) Field Descriptions
Name
0-31
FEDR[0:31]
Description
Flash ECC Data Register
This 32-bit register contains the data associated with the faulting access of the last, properly-enabled
flash ECC event. The register contains the data value taken directly from the data bus.
19-12
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor