PXD20RM Datasheet, PDF (852/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

21.4.1.3.2 Erase Suspend/Resume
The erase sequence may be suspended to allow read access to the FC. The erase sequence may also be
suspended to program (Erase-Suspended Program) the FC. A program started during erase suspend can in
turn be suspended. Only one erase suspend and one program suspend are allowed at a time during an
operation. It is not possible to erase during an erase suspend, or program during a program suspend. During
suspend, all reads to FC locations targeted for program and blocks targeted for erase return indeterminate
data. Programming locations in blocks targeted for erase during erase-suspended program may result in
corrupted data. Read While Write may also be used to read the array during an erase sequence providing
the read is to a partition not selected for erase.
An erase suspend can be initiated by changing the value of the MCR[ESUS] bit from a 0 to a 1.
MCR[ESUS] can be set to a 1 at any time when MCR[ERS] and MCR[EHV] are high and MCR[PGM] is
low. A 0 to 1 transition of MCR[ESUS] causes the module to start the sequence which places it in erase
suspend. The user must wait until MCR[DONE] = 1 before the module is suspended and further actions
are attempted. MCR[DONE] goes high no more than Tesus (Appendix A) after MCR[ESUS] is set to a 1.
Once suspended, the array may be read or a program sequence may be initiated (erase-suspended
program). Before initiating a program sequence the user must first clear MCR[EHV]. If a program
sequence is initiated the values of SOC specific shadow enable is recaptured. Once the erase-suspended
program is completed, the value of PEAS is returned to its’ “erase” value. FC reads while MCR[ESUS] =
1 from the block(s) being erased return indeterminate data.
The erase sequence is resumed by writing a logic 0 to MCR[ESUS]. MCR[EHV] must be set to a 1 and
MCR[PGM] must be cleared (in the event of an erase suspended program) before MCR[ESUS] can be
cleared to resume the operation. The module continues the erase sequence from one of a set of predefined
points. This may extend the time required for the erase operation.
WARNING
Repeated suspends at a high frequency may result in the operation timing
out, and the flash module will respond by completing the operation with a
fail code (MCR[PEG] = 0). The minimum time between erase suspends to
ensure this does not occur is 200uS.
WARNING
In an erase-suspended program, programming FC locations in blocks which
were being operated on in the erase may corrupt FC data.
21.4.2 Low Power mode
After Low Power mode is requested, the flash memory module turns off most current sources, although
logic/charge pumps to enable quick recovery to read are enabled for faster wake up time than Power Down
mode.
When in Low Power mode, register access is prevented. FC accesses are also prevented until Power Down
mode is exited. FC reads and writes may occur as soon as sleep mode is exited.
The flash module returns to its pre-Low Power state when enabled in all cases unless in the process of
executing a program or erase high voltage operation at the time of sleep. If the flash memory module is
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor