PXD20RM Datasheet, PDF (590/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 13-9. Timing parameters
Controls JEDEC
Timing parameter
parameter
(JEDEC spec)
Formulae
(all times in system bus
clock periods)
Description
RFC
RRD
RC
RAS
RCD
FAW
CCD
RTP
RP
RPA
WR1
WTR1
RTW1
t_RFC
t_RRD
t_RC
t_RAS
t_RCD
t_FAW
t_CCD
t_RTP
t_RP
t_RP
t_WR
t_WTR
—
RFC = t_RFC
REFRESH to ACTIVE or REFRESH to REFRESH
command interval.
RRD = t_RRD
RC = t_RC
RAS = t_RAS
RCD = t_RCD
FAW¹ = t_FAW
CCD² =
max(t_CCD,2) (32-bit mode)
max(t_CCD,4)(16-bit mode)
RTP³ =
t_RTP (32-bit mode, DDR2)
t_RTP+2 (16-bit mode, DDR2)
ACTIVE bank A to ACTIVE bank B command.
ACTIVE to ACTIVE (same bank) command.
ACTIVE to PRECHARGE command.
ACTIVE to READ or WRITE delay.
4-bank activate period.
CAS to CAS delay
Because time is needed for data to be sent over,
this time is minimum two clocks in 32-bit mode and
four clocks in 16-bit mode.
Read to precharge delay.
RTP is the read-to-precharge delay and t_RTP is the
internal read-to-precharge delay, hence, the
difference for 16-bit mode.
Figure 13-7 gives the details.
RP = t_RP
Precharge command period.
RPA⁴ = t_RP + 1 (8 bank device) Precharge all command period.
RPA = t_RP (4 bank device)
WR1 =
WL + t_WR + 2 (32-bit mode)
WL + t_WR + 4 (16-bit mode)
Write recovery time, measured in clocks between
write command and precharge command. For this
reason, WL (the write latency) and the length of the
actual write (2 or 4) need to be added to t_WR.
Figure 13-8 gives the details.
WTR1 =
WL + t_WTR + 2 (32-bit mode)
WL + t_WTR + 4 (16-bit mode)
Write to read time, measured in clocks between
write command and read command. For this
reason, WL (the write latency) and the length of the
actual write (2 or 4) need to be added to t_WTR.
Figure 13-9 gives the details.
RTW1 =
CL - WL + 2 + t_BTA (32-bit)
CL - WL + 4 + t_BTA (16-bit)
Read-to-write time, measured in clocks between
the read and write command. There is no limitation
on the DRAM on how to set this parameter. The
parameter should be set such that there is no
contention on the DQ data bus when switching
from read to write. Equation given at left tries to
come up with a formulae that defines the minimum
value of DRAM_TIME_RTW1 to avoid contention.
CL is the cas latency, WL is the write latency, and
t_BTA is the bus turn-around time. t_BTA is the
minimum dead time that needs to be put on the bus
between the driving the bus and the DRAM driving
the bus to take into account the transit delay on the
PCB, the pad delay, the DRAM skew, and the
on-chip delay.
13-10
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor