PXD20RM Datasheet, PDF (281/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

hclk
m0 request
m1 request
m4 request
m5 request
Highest
Priority
Requester
Address/Cntrl
owner
htrans
hready
1
2
3
4
Master 1 Master 4
XBAR Master 1
IDLE
NSEQ
Master 5
Master 4
NSEQ
5
6
7
Master 0
Master 5
NSEQ
Master 4
Master 0
NSEQ
8
9
10
Master 5
None
Master 4 Master 5 XBAR
NSEQ NSEQ IDLE
Figure 9-10. Round-robin mastership change
9.4.4.4.4 Slave Port State Machine Parking
If no master is currently making a request to the slave port then the slave port will be parked. It will park
in one of four places, dictated by the PCTL and PARK bits in the GPCR or AGPCR (depending on the
state of the sX_ampr_sel) and the locked state of the last master to access it.
If the last master to access the slave port ran a locked cycle and continues to run locked cycles even after
leaving the slave port the slave port will park on that master without regard to the bit settings in the GPCR
and without regard to pending requests from other masters. This is done so a master can run a locked
transfer to the slave port, leave it, and return to it and be guaranteed that no other master has had access to
it (provided the master maintains all transfers are locked transfers). If locking is not an issue for parking
the GPCR bits will dictate the parking method.
If the PCTL bits are set for “low power park” mode then the slave port will enter low power park mode. It
will not recognize any master as being in control of it and it will not select any master’s signals to pass
through to the slave bus. In this case all slave bus activity will effectively halt because all slave bus signals
being driven from the XBAR will be 0. This of course can save quite a bit of power if the slave port will
not be in use for some time. The down side is that when a master does make a request to the slave port it
will be delayed by one clock since it will have to arbitrate to acquire ownership of the slave port.
If the PCTL bits are set to “park on last” mode then the slave port will park on the last master to access it,
passing all that masters signals through to the slave bus. The XBAR will asynchronously force
htrans[1:0], hmaster[3:0], hburst[2:0] and hmastlock to 0 for all access that the master does not run to
the slave port. When that master access the slave port again it will not pay any arbitration penalty; however,
if any other master wishes to access the slave port a one clock arbitration penalty will be imposed.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-23