PXD20RM Datasheet, PDF (320/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• Classic SPI with CPHA = 0
• Classic SPI with CPHA = 1
• Modified transfer format with CPHA = 0
• Modified transfer format with CPHA = 1
A modified transfer format is supported to allow for high-speed communication with peripherals that
require longer setup times. The DSPI can sample the incoming data later than halfway through the cycle
to give the peripheral more setup time. The MTFE bit in the DSPIx_MCR selects between classic SPI
format and modified transfer format. The classic SPI formats are described in Section 10.9.5.1, Classic SPI
Transfer Format (CPHA = 0) and Section 10.9.5.2, Classic SPI Transfer Format (CPHA = 1). The
modified transfer formats are described in Section 10.9.5.3, Modified SPI Transfer Format (MTFE = 1,
CPHA = 0) and Section 10.9.5.4, Modified SPI Transfer Format (MTFE = 1, CPHA = 1).
In the SPI configuration, the DSPI provides the option of keeping the CS signals asserted between frames.
Refer to Section 10.9.5.5, Continuous Selection Format for details.
10.9.5.1 Classic SPI Transfer Format (CPHA = 0)
The transfer format shown in Figure 10-14 is used to communicate with peripheral SPI slave devices
where the first data bit is available on the first clock edge. In this format, the master and slave sample their
SIN_x pins on the odd-numbered SCK_x edges and change the data on their SOUT_x pins on the
even-numbered SCK_x edges.
SCK
(CPOL = 0)
SCK
(CPOL = 1)
Master and slave
sample
Master SOUT /
Slave SIN
Master SIN /
Slave SOUT
Master (CPHA = 0): TCF and EOQF are set and RXCTR counter
is updated at next to last SCK edge of frame (edge 15)
Slave (CPHA = 0): TCF is set and RXCTR counter is updated at
last SCK edge of frame (edge 16)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PCSx / SS
t_CSC
MSB first (LSBFE = 0): MSB Bit 6 Bit 5
LSB first (LSBFE = 1): LSB Bit 1 Bit 2
t_CSC = CSCS to SCK delay.
t_ASC = After SCK delay.
t_DT = Delay after transfer (minimum CS idle time).
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
t_ASC
t_DT
LSB ^tCSC
MSB
Figure 10-14. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 0, FMSZ = 8)
10-34
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor