PXD20RM Datasheet, PDF (1055/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

logic then evaluates the access against the effective permissions using the specification shown in
Table 28-10.
Table 28-10. Protection Violation Definition
Description
eff_r
gd[r]
Inputs
eff_rgd[ eff_rgd[
w]
x]
Output
Protection
Violation?
inst fetch read -
-
inst fetch read -
-
data read
0
-
data read
1
-
data write
-
0
data write
-
1
0
yes, no x permission
1 no, access is allowed
-
yes, no r permission
-
no, access is allowed
-
yes, no w permission
-
no, access is allowed
As shown in Figure 28-10, the output of the protection violation logic is the error signal.
The access evaluation macro then uses the hit_b and error signals to form two outputs. The combined
(hit_b | error) signal is used to signal the current access is not allowed and (~hit_b & error) is used as the
input to MPU_EDRn (error detail register) in the event of an error.
28.3.2 Putting It All Together and AHB Error Terminations
For each AHB slave port being monitored, the MPU performs a reduction-AND of all the individual (hit_b
| error) terms from each access evaluation macro. This expression then terminates the bus cycle with an
error and reports a protection error for three conditions:
1. If the access does not hit in any region descriptor, a protection error is reported.
2. If the access hits in a single region descriptor and that region signals a protection violation, then a
protection error is reported.
3. If the access hits in multiple (overlapping) regions and all regions signal protection violations, then
a protection error is reported.
The third condition reflects that priority is given to permission granting over access denying for
overlapping regions as this approach provides more flexibility to system software in region descriptor
assignments. For an example of the use of overlapping region descriptors, see Section 28.6, Application
information.
In event of a protection error, the MPU requires two distinct actions:
1. Intercepts the error during the AHB address phase (first cycle out of two) and cancels the
transaction before it is seen by the slave device.
2. Performs the required logic functions to force the standard 2-cycle AHB error response to properly
terminate the bus transaction and then provides the right values to the crossbar switch to commit
the AHB transaction to other portions of the platform.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
28-17