PXD20RM Datasheet, PDF (570/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

12.8.1.6 Modes of Operation Based on Sync Extraction
12.8.1.6.1 PDI input data (external sync mode)
In external sync mode the timing signals (HSYNC, VSYNC and, optionally, Date Enable) are provided to
the PDI input timing pins by the external video source.
External sync mode can be used in both normal mode and 8-bit narrow mode, but cannot be used in
conjunction with the YCbCr data format. In the instance that external sync and narrow mode is selected,
the external signals are used, and any timing information (EAV/SAV) embedded in the data stream is
ignored.
As in Figure 12-94, PDI data enable (PDI_DE) should be low during VSYNC and HSYNC pulse, VSYNC
front porch (FP_V) and back porch (BP_V), HSYNC front porch (FP_H) and back porch (BP_H). This is
valid for Data Enable Mode when the PDI_DE_EN bit is set in the DCU_MODE register (i.e. mode with
HSYNC, VSYNC, PDI_DE and PDI_PCLK as pin signals).
Pulse width, Front and back porch values should be picked from those programmed in DCULite registers.
In order to achieve lock, it must have same value as that of TFT screen. Front porch and back porch value
can be zero. Pulse width and TFT screen size parameters cannot be zero. In case they are programmed as
zero, it might lead to malfunctioning of the validation state machine.
As in Figure 12-93 HSYNC must occur during the VSYNC and vertical blanking period. The time
between 2 HSYNC should be same during VSYNC and vertical blanking as during the active line period.
As in Figure 12-93 the positive edge of HSYNC and VSYNC should be aligned. As in Figure 12-93 the
positive edge of the HSYNC and start of the vertical front/back porch should be aligned. The polarity of
HSYNC and VSYNC is selectable.
pdi_hsync
pdi_vsync
End of Last
active line
FP_V
(Vertical front porch)
Value = 2
(no of HSYNC)
Posedge of VSYNC
and HSYNC are aligned
Start of First Active line
PW_V
(Vertical pulse width)
Value = 2
(no of HSYNC)
BP_V
(Vertical back porch)
Value = 2
(no of HSYNC)
Vertical Blanking Period
Figure 12-93. Relationship between HSYNC and VSYNC in external synchronization
12-108
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor