PXD20RM Datasheet, PDF (1020/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

LINFlex2 regs
Frame (n)
Master-> Slave
Slave ->Slave
BIDR (4 bytes)
BDRL + BDRM
(4/8 bytes)
DMA transfer
RAM area
BIDR (4 bytes)
BDRL + BDRM
(4/8 bytes)
TCD (n)
Extended
Frame (n+1)
BIDR (4 bytes)
BDRL + BDRM
(8 bytes)
BIDR (4 bytes)
BDRL + BDRM
(8 bytes)
TCD (n+1)
Linked chain
Extended
Frame (n+1)
BDRL + BDRM
(4/8 bytes)
BDRL + BDRM
(4/8 bytes)
TCD (n+2)
1 DMA RX channel/ filter (TCD single and/or linked chain)
Figure 27-49. TCD chain memory map (slave node, RX mode)
The TCD chain of the DMA RX channel on a slave node supports:
• Master to Slave: reception of the data field.
• Slave to Slave: reception of the data field.
The register setting of the LINCR2, IFER, IFMR, and IFCR registers are given in Table 27-47.
Table 27-47. Register settings (slave node, RX mode)
LIN frame
LINCR2
IFER
IFMR
IFCR
Master to Slave DDRQ = 0 To enable an ID filter
or Slave to Slave DTRQ = 0 (Rx mode) for each
HTRQ = 0 DMA RX channel
- Identifier list mode
- Identifier mask mode
DFL = payload size
ID = address
CCS = checksum
DIR = 0 (RX)
The concept FSM to control the DMA Rx interface is shown in Figure 27-50. DMA RX FSM will move
to idle state if DMARXE[x] = 0 where x = IFMI – 1.
27-64
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor