PXD20RM Datasheet, PDF (1268/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Command
Table 35-48. Macronix Instruction Codes (continued)
Required Input Data / Parameters
Instruction
Code
Options
QSPI_ICR[ICO]
Address
[QSPI_SFAD]
1
Data
[TX Buffer]
Output Data
Status / Data
[RX Buffer]
Gang Block Lock
7Eh
Disable SO to output RY/BY
80h
Gang Block UnLock
98h
Continuous Mode
ADh
A23 - A0
S15 - S0 [16]
Enter Secured OTP
B1h
Enter 4byte Mode
B7h
Exit Secured OTP
C1h
1 _{The address bits are decided by the mode serial flash is working. For 32-bit extended address the bits used are A26 - A0,}
and for default 24-bit address mode the bits used are A23 - A0.
2 _{Denotes that ‘size’- times one byte is transferred on the serial flash data bus. Total number of bytes must be provided in}
the TX Buffer or can be read from the RX Buffer.
The QSPI_MCR[ICO] field is mapped to the different command options belonging to the complete SFM
Command which is then sent to the serial flash. This is shown in detail in the following tables. Table 35-49
shows the commands usable in all flash access modes, Table 35-50 the commands specific to the
Individual Flash Modes, and Table 35-51 the commands specific to the Parallel Flash Mode. All size
information is given in number of bytes. Note that the mapping reflects the bits which are actually sent to
the single serial flash device selected in the Individual Flash Mode or which are sent to each of the two
serial flash devices in the Parallel Flash Mode.
Table 35-49. ICO Field on Macronix Devices - All Flash Access Modes
Instruction
QSPI_ICR[ICO]
Code
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
01h
Size
02h
Size (bytes to be written)
05h
Size
32h
Size (bytes to be written)
35h
Size
03h
0Bh
3Bh
Individual Flash Access: Refer to Table 35-50
BBh
Parallel Flash Access: Refer to Table 35-51
6Bh
EBh
35-58
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor