PXD20RM Datasheet, PDF (810/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock
domains. Therefore, it may take some time to fully propagate its effects. The SOFT_RST bit remains
asserted while soft reset is pending, so software can poll this bit to know when the reset has completed.
Also, soft reset can not be applied while clocks are shut down in any of the low power modes. The low
power mode should be exited and the clocks resumed before applying soft reset.
The clock source (CLK_SRC bit) should be selected while the module is in Disable Mode. After the clock
source is selected and the module is enabled (MDIS bit negated), FlexCAN automatically goes to Freeze
Mode. In Freeze Mode, FlexCAN is un-synchronized to the CAN bus, the HALT and FRZ bits in MCR
Register are set, the internal state machines are disabled and the FRZ_ACK and NOT_RDY bits in the
MCR Register are set. The Tx pin is in recessive state and FlexCAN does not initiate any transmission or
reception of CAN frames. Note that the Message Buffers and the Rx Individual Mask Registers are not
affected by reset, so they are not automatically initialized.
For any configuration change/initialization it is required that FlexCAN is put into Freeze Mode (see
Section 20.5.9.1, Freeze mode). The following is a generic initialization sequence applicable to the
FlexCAN module:
• Initialize the Module Configuration Register
— Enable the individual filtering per MB and reception queue features by setting the BCC bit
— Enable the warning interrupts by setting the WRN_EN bit
— If required, disable frame self reception by setting the SRX_DIS bit
— Enable the FIFO by setting the FEN bit
— Enable the local priority feature by setting the LPRIO_EN bit
• Initialize the Control Register
— Determine the bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW
— Determine the bit rate by programming the PRESDIV field
— Determine the internal arbitration mode (LBUF bit)
• Initialize the Message Buffers
— The Control and Status word of all Message Buffers must be initialized
— If FIFO was enabled, the 8-entry ID table must be initialized
— Other entries in each Message Buffer should be initialized as required
• Initialize the Rx Individual Mask Registers
• Set required interrupt mask bits in the mask registers (for all MB interrupts) and in CTRL Register
(for Bus Off and Error interrupts)
• Negate the MCR[HALT] bit
Starting with the last event, FlexCAN attempts to synchronize to the CAN bus.
20.6.2 FlexCAN Addressing and RAM size configurations
There are 3 RAM configurations that can be implemented within the FlexCAN module. The possible
configurations are:
• For 16 MBs: 288 bytes for MB memory and 64 bytes for Individual Mask Registers
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor