PXD20RM Datasheet, PDF (871/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 22-10. Write byte strobes mapping
Input Write Byte Strobes WSTRB[7] WSTRB[6] WSTRB[5] WSTRB[4] WSTRB[3] WSTRB[2] WSTRB[1] WSTRB[0]
WD
HW
BY
Output Write Byte Strobes
0
0
0
WSTRB[7] WSTRB[6] WSTRB[5] WSTRB[4] WSTRB[3] WSTRB[2] WSTRB[1] WSTRB[0]
0
0
1
WSTRB[6] WSTRB[7] WSTRB[4] WSTRB[5] WSTRB[2] WSTRB[3] WSTRB[0] WSTRB[1]
0
1
0
WSTRB[5] WSTRB[4] WSTRB[7] WSTRB[6] WSTRB[1] WSTRB[0] WSTRB[3] WSTRB[2]
0
1
1
WSTRB[4] WSTRB[5] WSTRB[6] WSTRB[7] WSTRB[0] WSTRB[1] WSTRB[2] WSTRB[3]
1
0
0
WSTRB[3] WSTRB[2] WSTRB[1] WSTRB[0] WSTRB[7] WSTRB[6] WSTRB[5] WSTRB[4]
1
0
1
WSTRB[2] WSTRB[3] WSTRB[0] WSTRB[1] WSTRB[6] WSTRB[7] WSTRB[4] WSTRB[5]
1
1
0
WSTRB[1] WSTRB[0] WSTRB[3] WSTRB[2] WSTRB[5] WSTRB[4] WSTRB[7] WSTRB[6]
1
1
1
WSTRB[0] WSTRB[1] WSTRB[2] WSTRB[3] WSTRB[4] WSTRB[5] WSTRB[6] WSTRB[7]
22.4.6 Frame buffer color depth converter
To save space in on-chip GRAM, the GXG implements a color depth converter to reduce GFX2D 32-bpp
frame buffers to 24-bpp before storing into RAM. Since conversion is only done for frame buffers, the
GXG uses the address filter to detect frame buffer access. Each window of the address filter can be enabled
for color depth conversion by programming the respective MODE bits. The GXG supports conversions
only for 32-byte transactions with 16-byte aligned input addresses. The GFX2D stride must match the
GXG stride which is adjusted using the GXGSTRIDE register.
During the address phase of the transaction, the input address from the GFX2D is translated to an output
address in physical RAM according to Equation .
OFS23:0 = INPADR31:2 – FIRSTn31:2
OUTADR = BASEn + 4  OFS23:12 + Z  STRIDEn + 3  OFS11:0
INPADR – Input address from GFX2D to be translated.
FIRSTn – Window first address. See Section 22.3.2.3, Window First
Address (GXGFRST0-3).
OFS – Intermediate offset calculation
BASEn – Destination base address. See Section 22.3.2.2, Window
Destination Base Address (GXGBASE0-3).
STRIDEn – Width of the frame buffer in physical RAM. See Section 22.3.2.1,
Window Configuration (GXGCNFG0-3).
OUTADR – Translated output address to physical RAM.
Z – Value of GXGSTRIDE register (0 to 6). See Section 22.3.2.5,
GFX2D Stride Setting (GXGSTRIDE).
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
22-11