PXD20RM Datasheet, PDF (59/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

channels. This implementation is utilized to minimize the overall block size. The eDMA module provides
the following features:
• 16 channels support independent 8-, 16- or 32-bit single value or block transfers
• Supports variable sized queues and circular queues
• Source and destination address registers are independently configured to post-increment or remain
constant
• Each transfer is initiated by a peripheral, CPU, periodic timer interrupt or eDMA channel request
• Each DMA channel can optionally send an interrupt request to the CPU on completion of a single
value or block transfer
• DMA transfers possible between system memories, QuadSPI, RLE Decoder, SPIs, I²C, ADC,
eMIOS and General Purpose I/Os (GPIOs)
• Programmable DMA Channel Mux allows assignment of any DMA source to any available DMA
channel with up to a total of 64 potential request sources.
1.5.5 Interrupt Controller (INTC)
The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests,
suitable for statically scheduled hard real-time systems.
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral
to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC
provides a unique vector for each interrupt request source for quick determination of which ISR needs to
be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the
execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request,
the priority of each interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC
supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the
priority can be raised temporarily so that all tasks which share the resource can not preempt each other.
Multiple processors can assert interrupt requests to each other through software settable interrupt requests.
These same software settable interrupt requests also can be used to break the work involved in servicing
an interrupt request into a high priority portion and a low priority portion. The high priority portion is
initiated by a peripheral interrupt request, but then the ISR asserts a software settable interrupt request to
finish the servicing in a lower priority ISR. Therefore these software settable interrupt requests can be used
instead of the peripheral ISR scheduling a task through the RTOS. The INTC provides the following
features:
• Unique 9-bit vector for each of the possible 128 separate interrupt sources
• Eight software triggerable interrupt sources
• 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
• Ability to modify the ISR or task priority.
— Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing
shared resources.
• External non maskable interrupt directly accessing the main CPU critical interrupt mechanism
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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