PXD20RM Datasheet, PDF (1172/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

31.5.1 MH_MMU_CONFIG
Offset: 0x040
Access: User read/write
Field
31–26
25–24
23–22
21–20
19–18
17–16
15–14
13–12
11–10
9–8
7–6
5–4
3–2
1
0
Reset
Description
0x0 Reserved
0x0 Specifies PAw client behavior for MMU lookups. See Table 31-17.
0x0 Specifies TCr client behavior for MMU lookups. See Table 31-17.
0x0 Specifies VGTr1 client behavior for MMU lookups. See Table 31-17.
0x0 Specifies VGTr0 client behavior for MMU lookups. See Table 31-17.
0x0 Specifies CPr4 client behavior for MMU lookups. See Table 31-17.
0x0 Specifies CPr3 client behavior for MMU lookups. See Table 31-17.
0x0 Specifies CPr2 client behavior for MMU lookups. See Table 31-17.
0x0 Specifies CPr1 client behavior for MMU lookups. See Table 31-17.
0x0 Specifies CPr0 client behavior for MMU lookups. See Table 31-17.
0x0 Specifies CPw client behavior for MMU lookups. See Table 31-17.
0x0 Specifies RBw client behavior for MMU lookups. See Table 31-17.
0x0 Padding
0x0 SPLIT_MODE_ENABLE. Reserves 8 translation buffer entries for use by the TC client
0x0 MMU_ENABLE. Enables MMU; if disabled all MMU checks are bypassed and PA = VA
Table 31-17. MMU Behavior
Value
Description
0x0 Never translate, PA = VA
0x1 Translate if VA is in VA range, otherwise PA = VA
0x2 Only translate if VA is in VA range, else page fault
31.5.2 MH_MMU_VA_RANGE
Offset: 0x041
Access: User read/write
Field Reset
Description
31–12
11–0
0x0 Virtual Base address (VA_BASE[31:12]) aligned to a 4kB page boundary (VA_BASE[11:0]=0).
0x0 Number of 64 KB regions mapped, up to 256MB
31.5.3 MH_MMU_PT_BASE
31-40
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor