PXD20RM Datasheet, PDF (322/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

The master initiates the transfer by asserting the CSx signal to the slave. After the t_CSC delay has elapsed,
the master generates the first SCK_x edge and at the same time places valid data on the master SOUT_x
pin. The slave responds to the first SCK_x edge by placing its first data bit on its slave SOUT_x pin.
At the second edge of the SCK_x the master and slave sample their SIN_x pins. For the rest of the frame
the master and the slave change the data on their SOUT_x pins on the odd-numbered clock edges and
sample their SIN_x pins on the even-numbered clock edges. After the last clock edge occurs a delay of
t_ASC is inserted before the master negates the CSx signal. A delay of t_DT is inserted before a new frame
transfer can be initiated by the master.
For CPHA = 1 the master EOQF and TCF and slave TCF are set at the last serial clock edge (edge 16) of
Figure 10-15. For CPHA = 1 the master and slave RXCTR counters are updated on the same clock edge.
10.9.5.3 Modified SPI Transfer Format (MTFE = 1, CPHA = 0)
In this modified transfer format both the master and the slave sample later in the SCK period than in classic
SPI mode to allow for delays in device pads and board traces. These delays become a more significant
fraction of the SCK period as the SCK period decreases with increasing baud rates.
NOTE
For the modified transfer format to operate correctly, you must thoroughly
analyze the SPI link timing budget.
The master and the slave place data on the SOUT_x pins at the assertion of the CSx signal. After the CSx
to SCK_x delay has elapsed the first SCK_x edge is generated. The slave samples the master SOUT_x
signal on every odd numbered SCK_x edge. The slave also places new data on the slave SOUT_x on every
odd numbered clock edge.
The master places its second data bit on the SOUT_x line one system clock after odd numbered SCK_x
edge. The point where the master samples the slave SOUT_x is selected by writing to the SMPL_PT field
in the DSPIx_MCR. Table 10-24 lists the number of system clock cycles between the active edge of
SCK_x and the master sample point for different values of the SMPL_PT bit field. The master sample point
can be delayed by one or two system clock cycles.
Table 10-24. Delayed Master Sample Point
SMPL_PT
Number of System Clock Cycles between
Odd-numbered Edge of SCK and Sampling of SIN
00
0
01
1
10
2
11
Invalid value
Figure 10-16 shows the modified transfer format for CPHA = 0. Only the condition where CPOL = 0 is
illustrated. The delayed master sample points are indicated with a lighter shaded arrow.
10-36
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor