PXD20RM Datasheet, PDF (763/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 19-12. RAM Syndrome Mapping for Single-Bit Correctable Errors (continued)
RESR[0:7]
0x24
0x26
0x28
0x2a
0x2c
0x58
0x30
0x32
0x34
0x64
0x38
0x62
0x70
0x60
0x40
0x42
0x44
0x46
0x48
0x4a
0x4c
0x03,0x05........0x4d
> 0x4d
Data Bit in Error
DATA ODD BANK[19]
DATA ODD BANK[18]
DATA ODD BANK[17]
DATA ODD BANK[16
DATA ODD BANK[15]
DATA ODD BANK[14]
DATA ODD BANK[13]
DATA ODD BANK[12]
DATA ODD BANK[11]
DATA ODD BANK[10]
DATA ODD BANK[9]
DATA ODD BANK[8]
DATA ODD BANK[7]
DATA ODD BANK[6]
ECC ODD[6]
DATA ODD BANK[5]
DATA ODD BANK[4]
DATA ODD BANK[3]
DATA ODD BANK[2]
DATA ODD BANK[1]
DATA ODD BANK[0]
Multiple bit error
Multiple bit error
19.4.2.12 RAM ECC Master Number Register (REMR)
The REMR is a 4-bit register for capturing the AXBS bus master number of the last, properly-enabled ECC
event in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in
the RAM causes the address, attributes and data associated with the access to be loaded into the REAR,
RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status
Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 19-11 and Table 19-13 for the RAM ECC Master Number Register definition.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
19-15