PXD20RM Datasheet, PDF (1023/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• Adsorb the latency, following a DMA request (due to the DMA arbitration), to move data from the
RAM to the FIFO
• Use low priority DMA channels
• Support the UART baud rate (2 Mb/s) without underrun events
The Tx FIFO size is:
• 4 bytes in 8-bit data format
• 2 half-words in 16-bit data format
A DMA request is triggered by FIFO not full (TX) status signals.
The concept FSM to control the DMA TX interface is shown in Figure 27-52. DMA TX FSM will move
to idle state if DMATXE[0] = 0.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
27-67