PXD20RM Datasheet, PDF (278/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

The muxes also have an override signal which is used by the slave port to asynchronously force IDLE
cycles onto the slave bus. When the state machine forces an IDLE cycle it zeros out htrans and hmastlock,
making sure the slave bus sees a valid IDLE cycle being run by the XBAR.
The enable to the mux controlling htrans also contains an additional control signal from the state machine
so that a NSEQ transaction can be forced. This is done any time the slave port switches masters to ensure
that no IDLE-SEQ, BUSY-SEQ or NSEQ-SEQ transactions are seen on the slave port when they shouldn’t
be. If the state machine indicates to run both an IDLE and an NSEQ cycle, the IDLE directive will have
priority.
NOTE
IDLE-SEQ is in fact an illegal access, but a possible scenario given the
multi-master environment in the XBAR unless corrected by the XBAR.
9.4.4.3 Slave Port Registers
There is a register control block at the same level of the master port and slave port instantiations in the
XBAR. This control block ensures that all accesses are 64-bit supervisor accesses before passing them on
to the master and slave ports.
The registers in the slave port are only those registers associated with this particular slave port. The read
and write interface for the registers is a quasi-IP bus interface. It is not a full IP bus interface at this level
because not all the IP bus signals are routed this deep in the design.
The register outputs are connected directly to the slave state machine with the sX_ampr_sel input
determining which priority register values, halt priority value, arbitration algorithm and parking control
bits are passed to the state machine. The registers can be read from an unlimited number of times. The
registers can only be written to as long as the RO bit is written to 0 in the SGPCR, once it is written to a 1
only a hardware reset will allow the registers to be written again.
9.4.4.4 Slave Port State Machine
9.4.4.4.1 Slave Port State Machine States
At the heart of the slave port is the state machine. The state machine is simplicity itself, requiring only four
states - steady state, transition state, transition hold state and hold state. Either the slave port is owned
by the same master it was in the last clock cycle (either by active use or by parking), it is transitioning to
a new master (either for active use or parking), it is transitioning to a new master during wait states or it is
being held on the same master pending a transition to a new master.
9.4.4.4.2 Slave Port State Machine Arbitration
The real work in the state machine is determining which master port will be in control of the slave port in
the next clock cycle, the arbitration. Each master is programmed with a fixed 3 bit priority level. A fourth
priority bit is derived from the mX_high_priority inputs on the master ports, effectively making each
master’s priority level a 4 bit field with mX_high_priority being the MSB. The XBAR uses these bits in
determining priority levels when programmed for fixed priority mode of operation or when one of the
enabled mX_high_priority inputs is asserted.
9-20
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor