PXD20RM Datasheet, PDF (1249/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

35.5.4 Power Saving Features
The QuadSPI supports three power-saving strategies:
• Stop Mode
• Module Disable Mode - Clock gating of non-memory mapped logic
• Clock gating of slave bus signals and clock to memory-mapped logic
Like all power saving features the Stop Mode requires logic external to the QuadSPI module for power
management and clock gating control. Figure 35-18 shows an example on how the QuadSPI power saving
features can be used:
Power
Management
Block
system clock
ipg_enable_clk
Forced to 0
ipg_stop_ack
ipg_stop
& ^ipg_clk
ips_addr,
ips_byte_en,
ips_rwb,
ips_wdata
&
&
&
&
Power Saving
Logic
Non-Memory Mapped Area
&
D_RSVD
MDIS
Memory Mapped Area
QuadSPI
ips_module_en
DQ
&
ipg_clk_s
Figure 35-18. power Saving Mode Concept of QuadSPI module
35.5.4.1 Stop Mode
The QuadSPI has a dedicated low power mode managed by the Mode Entry module. When the Mode Entry
module requests the QuadSPI module to enter low power mode, the QuadSPI block waits until the
following conditions are met before completing the mode transition:
• QSPI_SFMSR[BUSY] = 0 and
• QSPI_SFMSR[AHBTRN] = 0 and
• QSPI_RBSR[RDBFL] = 0 and
• QSPI_SFMSR[RXDMA] = 0
• None of the flags in the QSPI_SFMFR register enabled as interrupts is set
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
35-39