PXD20RM Datasheet, PDF (372/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Offset: 0x1DC
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0
W
BP_H
00
PW_H[0:3]
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
16
R
W
Reset 0
Field
1–9
BP_H
12–20
PW_H
23–31
FP_H
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PW_H[4:8]
00
FP_H
001100000000011
Figure 11-18. HSYN_PARA Register
Table 11-20. HSYN_PARA Field Descriptions
Description
HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1.
HSYNC active pulse width (in pixel clock cycles).
HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1.
11.3.4.16 VSYN_PARA Register
Figure 11-19 represents the VSYN_PARA register. VSYN_PARA register sets timing parameters related
to the vertical synchronization signal generation. The fields FP_V, BP_V, and PW_V stand for VSYNC
signal front-porch, back-porch, and active pulse width, respectively.
Offset: 0x1E0
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0
W
BP_V
00
PW_V[0:3]
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PW_V[4:8]
W
00
FP_V
Reset 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1
Figure 11-19. VSYN_PARA Register
11-38
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor