PXD20RM Datasheet, PDF (219/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

8.3.3.1.15 Auxiliary Clock 4 Divider Configuration Register (CGM_AC4_DC)
Address 0xC3FE_03A4
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
000
DE0
W
DIV0
00000000
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-17. Auxiliary Clock 4 Divider Configuration Register (CGM_AC4_DC)
This register controls the auxiliary clock 4 divider.
Table 8-18. CGM_AC4_DC field descriptions
Field
Description
DE0
DIV0
Divider 0 Enable
0 Disable auxiliary clock 4 divider 0
1 Enable auxiliary clock 4 divider 0
Divider 0 Division Value — The resultant DCULite clock will have a period DIV0 + 1 times that of
auxiliary clock 4. If the DE0 is set to 0 (Divider 0 is disabled), any write access to the DIV0 field is ignored
and the DCULite clock remains disabled.
8.3.4 Functional description
8.3.4.1 System clock generation
Figure 8-19 shows the block diagram of the system clock generation logic. The MC_ME provides the
system clock select and switch mask (see MC_ME documentation for more details), and the MC_RGM
provides the safe clock request (see MC_RGM documentation for more details). The safe clock request
forces the selector to select the 16 MHz int. RC osc. as the system clock and to ignore the system clock
select.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-23