PXD20RM Datasheet, PDF (1122/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Nexus 0x0003
Reg:
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
EWC
0
0
0
0
0
0
0
0
W
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23 24 25 26 27 28 29 30 31
R₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 30-6. Development Control Register 2 (DC2)
Table 30-6. DC2 Field Descriptions
Field
Description
0–7
EWC[7:0]
EVTO Watchpoint Configuration. Any or all of the bits in EWC may be set to configure the EVTO
watchpoint.
00000000 No Watchpoints trigger EVTO
1XXXXXXX Watchpoint #0 (IAC1 from Nexus1) triggers EVTO.
X1XXXXXX Watchpoint #1 (IAC2 from Nexus1) triggers EVTO.
XX1XXXXX Watchpoint #2 (IAC3 from Nexus1) triggers EVTO.
XXX1XXXX Watchpoint #3 (IAC4 from Nexus1) triggers EVTO.
XXXX1XXX Watchpoint #4 (DAC1 from Nexus1) triggers EVTO.
XXXXX1XX Watchpoint #5 (DAC2 from Nexus1) triggers EVTO.
XXXXXX1X Watchpoint #6 (DCNT1 from Nexus1) triggers EVTO.
XXXXXXX1 Watchpoint #7 (DCNT2 from Nexus1) triggers EVTO.
8–31 Reserved.
NOTE
The EOC bits in DC1 must be programmed to trigger EVTO on watchpoint
occurrence for the EWC bits to have any effect.
30.6.2.4 Development Status Register (DS)
The development status register is used to report system debug status. When debug mode is entered or
exited, or a CPU-defined low-power mode is entered, a debug status message is transmitted with
DS[31:24]. The external tool can read this register at any time.
30-10
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor