PXD20RM Datasheet, PDF (585/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Field
H_DQSDLY
Q_DQSDLY
WDLY[2:0]
EODT
ODT
FIFO_OVP
FIFO_UVP
FIFO_OVEN
FIFO_UVEN
Table 13-2. DRAMC_SCR field descriptions (continued)
Description
This field is an extra field to control the expected read delay between issuing the read command and
getting read data from the DRAM. This field offers 1/2 system bus clock granularity when
programming the delay. See description of field RDLY for details.
This field is an extra field to control the expected read delay between issuing the read command, and
getting read data from the DRAM. This field offers 1/4 system bus clock granularity when
programming the delay. See the description of the RDLY bitfield.
This field controls the write latency (WL) for write commands.
WDLY[2:0]
Write Latency (CSB Clocks)
0b001
1
0b010
2
0b011
3
0b100
4
This bit needs to be set if write latency is 1 (WDLY[2:0] = 001) and on die termination is used with
DDR2 DRAM. It makes sure the DRAMC asserts the ODT signal going to the DRAM one clock
ahead of issuing the write command.
This bit controls on-die termination (ODT) in the controller. If this bit is 1, the internal pads generate
ODT during read. If the bit is 0, no ODT is provided. The ODT in the DRAM is controlled via the
DRAM internal configuration registers. Please consult DRAM data sheet for it.
These bits indicate timing errors and allow the generation of interrupts when these errors occur. The
DRAMC has two interrupts: FIFO OV pending and FIFO UV pending. These interrupts are set on
overflow or underflow of the FIFO in the read block. When a read command is sent to the DRAM, it
is entered into a FIFO. The DRAM is expected to answer by sending back the read data with some
up and down edges on the DQS lines (the DQS strobes) used to clock the data. The DRAMC clocks
the read data with the DQS strobes supplied by the DRAM and retrieves the read command from
the FIFO after receiving the correct number of read strobes. When the read data strobes returned
by the DRAM do not match the expectations of the controller, the FIFO may underflow (if too many
DQS strobes are coming back from the DRAM) or overflow (if not enough DQS strobes are coming
back). These underflows and overflows are the result of problems with the DRAM interface or
incorrect parameter settings in the controller or the DRAM. Care has been taken during the design
of the DRAMC not to enter a hang-up state when this occurs. However, read data is corrupt and CPU
is informed via the FIFO overflow and FIFO underflow interrupts. The issue is also discussed in
Section 13.4.7, Bus Interface.
• FIFO_OV_PENDING and FIFO_UV_PENDING signal to the CPU if an overflow or underflow
interrupt is pending. Write “1“ to these bits clears the corresponding interrupt.
• FIFO_OV_EN and FIFO_UV_EN bits are interrupt enable bits. If the pending + enable bit is set
at the same time, the interrupt is sent to the CPU.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
13-5