PXD20RM Datasheet, PDF (1353/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Field
Description
10
FEIECH2
9
FEIECH1
8
FEIECH0
7
FOIECH3
6
FOIECH2
5
FOIECH1
4
FOIECH0
3
FUIECH3
2
FUIECH2
1
FUIECH1
0
FUIECH0
FIFO Empty Interrupt Enable for Channel 2.
FIFO Empty Interrupt Enable for Channel 1.
FIFO Empty Interrupt Enable for Channel 0.
FIFO Overflow Interrupt Enable for Channel 3.
FIFO Overflow Interrupt Enable for Channel 2.
FIFO Overflow Interrupt Enable for Channel 1.
FIFO Overflow Interrupt Enable for Channel 0.
FIFO Underflow Interrupt Enable for Channel 3.
FIFO Underflow Interrupt Enable for Channel 2.
FIFO Underflow Interrupt Enable for Channel 1.
FIFO Underflow Interrupt Enable for Channel 0.
39.6.2.26 SGM Interrupt Control Register (SGMIC)
The SGMIC register enables and controls the interrupts associated with each sound channel.
SGM Register Base + 0x00DC
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
TOIE
W
0
0
0
0
0
0 _{PDIE PDIE PDIE PDIE RDIE RDIE RDIE RDIE}
CH3 CH2 CH1 CH0 CH3 CH2 CH1 CH0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R _{EORI EORI EORI EORI EOAI EOAI EOAI EOAI EONI EONI EONI EONI PCIE PCIE PCIE PCIE}
W ^{ECH3 ECH2 ECH1 ECH0 ECH3 ECH2 ECH1 ECH0 ECH3 ECH2 ECH1 ECH0 CH3 CH2 CH1 CH0}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 39-27. SGM Interrupt Control Register (SGMIC)
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
39-29