PXD20RM Datasheet, PDF (267/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

9.3.2.2 Slave General Purpose Control Register
The Slave General Purpose Control Register (SGPCR) controls several features of each slave port.
The Read Only (RO) bit will prevent any registers associated with this slave port from being written to
once set. This bit may be written with 0 as many times as the user desires, but once it is written to a 1 only
a reset condition will allow it to be written again.
The Halt Low Priority (HLP) bit will set the priority of the max_halt_request input to the lowest possible
priority for initial arbitration of the slave ports. By default it is the highest priority. Setting this bit will not
effect the max_halt_request from attaining highest priority once it has control of the slave ports.
The PCTL bits determine how the slave port will park when no master is actively making a request. The
available options are to park on the master defined by the PARK bits, park on the last master to use the
slave port, or go into a low power park mode which will force all the outputs of the slave port to inactive
states when no master is requesting an access. The low power park feature can result in an overall power
savings if a the slave port is not saturated; however, it will force an extra clock of latency whenever any
master tries to access it when it is not in use because it will not be parked on any master.
The PARK bits determine which master the slave will park on when no master is making an active request
and the max_halt_request input is negated. Please use caution to only select master ports that are actually
present in the design. If the user programs the PARK bits to a master not present in the current design
implementation undefined behavior will result.
SGPCRn
Slave General Purpose Control Register n
Addr
$BASE + 0x010 + n*100
Wait State: 0
Access: S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RO HLP
HPE HPE HPE HPE HPE HPE HPE HPE
76543210
TYPE: rw rw r
r
r
r
r
r rw rw rw rw rw rw rw rw
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Note: Once the RO bit is written to a 1, only hardware reset will return it to a 0.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ARB
PCTL
PARK
TYPE: r
r
r
r
r
r rw rw r
r rw rw r rw rw rw
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Note: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Note: for n = 0 to 7
Figure 9-4. Slave General Purpose Control Register n
PXD20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
9-9
Preliminary—Subject to Change Without Notice