PXD20RM Datasheet, PDF (152/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 5-5. Interrupt Status Register (ISR) field descriptions (continued)
Field
29
30
31
Description
End of Injected Chain Conversion interrupt (JECH) flag. It is the interrupt of the digital end of chain
conversion for the injected channel; active when set. When this bit is set, a JECH interrupt has occurred.
End of Channel Conversion interrupt (EOC) flag. It is the interrupt of the digital end of conversion. When
this bit is set, an EOC interrupt has occurred.
End of Chain Conversion interrupt (ECH) flag. It is the interrupt of the digital end of chain conversion.
When this bit is set, an ECH interrupt has occurred.
5.3.3.2 Channel Pending Registers (CEOCFR[1..2])
The 0 to 31 range shown below is the maximum range for the channel type. For the exact number of
available channels, please refer to Table 5-1.
CEOCFR1 = End of conversion pending interrupt for channel 32 to 63 (extended internal channels)
CEOCFR2 = End of conversion pending interrupt for channel 64 to 95 (external channels)
Address: Base + 0x0018
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_
CH63 CH62 CH61 CH60 CH59 CH58 CH57 CH56 CH55 CH54 CH53 CH52 CH51 CH50 CH49 CH48
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_ EOC_
CH47 CH46 CH43 CH44 CH43 CH42 CH41 CH40 CH39 CH38 CH37 CH36 CH35 CH34 CH33 CH32
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-5. Channel Pending Register 1 (CEOCFR1)
5-10
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor