PXD20RM Datasheet, PDF (992/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 27-19. UARTSR field descriptions (continued)
Field
Description
RMB
FEF
BOF
RPS
WUF
TO
DRFRFE
DTFTFF
NF
Release Message Buffer
0: Buffer is free
1: Buffer ready to be read by software. This bit must be cleared by software after reading data received
in the buffer.
This bit is cleared by hardware in Initialization mode.
Framing Error Flag
This bit is set by hardware and indicates to the software that LINFlexD has detected a framing error
(invalid stop bit).
FIFO/buffer overrun flag
This bit is set by hardware when a new data byte is received and the RMB bit is not cleared in UART
buffer mode. In UART FIFO mode, this bit is set when there is a new byte and the Rx FIFO is full. In
UART FIFO mode, once Rx FIFO is full, the new received message is discarded regardless of the
value of LINCR1[RBLM].
If LINCR1[RBLM] = 1, the new byte received is discarded.
If LINCR1[RBLM] = 0, the new byte overwrites buffer.
This field can be cleared by writing a 1 to it. An interrupt is generated if LINIER[BOIE] is set.
LIN Receive Pin State
This bit reflects the current status of LINRX pin for diagnostic purposes.
Wake-up Flag
This bit is set by hardware and indicates to the software that LINFlexD has detected a falling edge on
the LINRX pin in Sleep mode.
This bit must be cleared by software. It is reset by hardware in Initialization mode.
An interrupt i generated if WUIE bit in LINIER is set.
Timeout
The LINFlexD controller sets this field when a UART timeout occurs — that is, when the value of
UARTCTO becomes equal to the preset value of the timeout (UARTPTO register setting). This field
should be cleared by software. The GCR[SR] field should be used to reset the receiver FSM to idle
state in case of UART timeout for UART reception depending on the application both in buffer and
FIFO mode.
An interrupt is generated when LINIER[DBEIETOIE] is set on the Error interrupt line in UART mode.
Data reception completed flag / Rx FIFO empty flag
The LINFlexD controller sets this field as follows:
• In UART buffer mode (RFBM = 0), it indicates that the num ber of bytes programmed in RDFL has
been received. This field should be cleared by software. An interrupt is generated if LINIER[DRIE]
is set. This field is set in case of framing error, parity error, or overrun. This field reflects the same
value as in LINESR when in Initialization mode and UART bit is set.
• In UART FIFO mode (RFBM = 1), it indicates that the Rx FIFO is empty. This field is a read-only
field used internally by the DMA Rx interface.
Data transmission completed flag / Tx FIFO full flag
The LINFlexD controller sets this field as follows:
• In UART buffer mode (TFBM = 0), it indicates that the data transmission is completed. This field
should be cleared by software. An interrupt is generated if LINIER[DTIE] is set. This field reflects
the same value as in LINESR when in Initialization mode and UART bit is set.
• In UART FIFO mode (TFBM = 1), it indicates that the Tx FIFO is full. This field is a read-only field
used internally by the DMA Tx interface.
Noise Flag
This bit is set by hardware when noise is detected on a received character. This bit is cleared by
software.
27-36
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor