PXD20RM Datasheet, PDF (157/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

5.3.4 DMA registers
5.3.4.1 DMA Enable Register (DMAE)
The DMA Enable (DMAE) register sets up the DMA for use with the ADC.
Address: Base + 0x0040
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
R0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-12. DMA Enable Register (DMAE)
Table 5-11. DMA Enable Register (DMAE) field descriptions
Field
0:29
30
31
Description
Reserved
Write of any value has no effect, read value is always 0.
DCLR: DMA clear sequence enable
0 DMA request cleared by Acknowledge from DMA controller
1 DMA request cleared on read of data registers
DMAEN: DMA global enable
0 DMA feature is disabled.
1 DMA feature is enabled.
29
30
31
0 _{DCL DMA}
R EN
000
5.3.4.2 DMA Channel Select Register (DMAR[1..2])
The 0 to 31 range shown below is the maximum range for the channel type. For the exact number of
available channels, please refer to Table 5-1.
DMAR1 = Enable bits for channels 32 to 63 (extended internal channels)
DMAR2 = Enable bits for channels 64 to 95 (external channels)
Reset value: 0x0000_0000
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
5-15