PXD20RM Datasheet, PDF (235/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

8.5.4 Memory map¹
Table 8-25 shows the memory map locations. Addresses are given as offsets of the module base address.
Table 8-25. FMPLL Memory Map
Address
Base:
0xC3FE00A0 (FMPLL0)
0xC3FE00C0 (FMPLL1)
0x0000
0x0004
Register
Control register (CR)
Modulation register (MR)
Access Location
R/W
Special
on page 8-39
on page 8-42
8.5.5 Register description
The PLL operation is controlled by two registers. Those registers can only be written in supervisor mode.
8.5.5.1 Control register (CR)
Offset 0x0000
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R₀
0
IDF
ODF
0
NDIV
W
Reset ₀
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R₀
0
0
0
0
0
0
unlock 0 i_lock s_lock
pll_fail 0
en_pll _{mode _once}
pll_fail _{_flag}
_sw
_mask
W
w1c
w1c
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 8-26. Control register (CR)
Table 8-27. CR field descriptions
Field
IDF
ODF
NDIV
Description
The value of this field sets the PLL Input division factor as described in Table 8-28. The reset value
is set during integration.
The value of this field sets the PLL Output division factor as described in Table 8-29. The reset value
is set during integration.
The value of this field sets the PLL Loop division factor as described in Table 8-30. The reset value
is set during integration.
1.FMPLL_x are mapped through the ME_CGM Register Slot
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-39