PXD20RM Datasheet, PDF (246/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

8.6.4.2 Frequency Display Register (CMU_FDR)
.
Address offset: 0x04
Reset value: 0x00000000
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
reserved
FD[19:16]
r
r
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FD[15:0]
r
Table 8-38. Frequency Display Register (CMU_FDR)
Table 8-39. Frequency Display Register (CMU_FDR) field descriptions
Field
12-31
FD
Description
Measured frequency bits
This register displays the measured frequency FRC with respect to FOSC. The measured
value is given by the following formula: FRC = (FOSC * MD) / n, Where n is the value in
CMU_FDR register
8.6.4.3 High Frequency Reference Register FMPLL0 (CMU_HFREFR)
Address offset: 0x08
Reset value: 0x00000FFF
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
reserved
r
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
HFREF[11:0]
r
rw
Table 8-40. High Frequency Reference Register FMPLL0
Table 8-41. High Frequency Reference Register FMPLL0 field descriptions
Field
20-31
HFREF
Description
High Frequency reference value
These bits determine the high reference value for the FMPLL0 clock. The reference value
is given by: (HFREF[11:0]/16) * (FRC_fast/4).
8-50
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor