PXD20RM Datasheet, PDF (259/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Chapter 9
Crossbar Switch (XBAR)
9.1 Information specific to this device
This section presents device-specific parameterization, customization, and feature availability information
not specifically referenced in the remainder of this chapter.
9.1.1 Device-specific block diagram
Figure 9-1 shows the simplified block diagram for the PXD20.
z4d core
(instruction)
M0
z4d core
(data)
M1
eDMA
M2
GFX2D
M3
VIU2
M4
DCULite
M5
DCU3
M6
Crossbar Switch
Master modules
Slave modules
Flash memory
(instruction)
S0
Flash memory
S1
SRAM
S2
Graphics RAM
(GFX2D)
S3
Graphics RAM
S4
Unused*
S5
QuadSPI
RLE
S6
PBRIDGE
S7
* DRAM accesses do not go through the XBAR.
Figure 9-1. Device-specific block diagram
9.1.2 XBAR Master ID Numbers
The XBAR module refers to individual masters by their physical master port number. Other modules such
as MPU and SWT use the master IDs. This is different from the physical master port numbers which are
in Figure 9-1 above.
Table 9-1. XBAR Master ID Numbers
Master
CPU (instruction)
CPU (Data)
eDMA
GFX2D
DCULite
Master ID Number
0
0
2
3
4
XBAR Port ID
0
1
2
3
4
PXD20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
9-1
Preliminary—Subject to Change Without Notice