PXD20RM Datasheet, PDF (1223/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Address: QSPI_BASE + 0x004
Write: Anytime
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0 0 0
W
NDC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Figure 35-4. Latency Configuration Register (QSPI_LCR)
Table 35-8. QSPI_LCR Field Descriptions
Field
Description
NDC¹
Number of dummy cycles to be inserted during command execution.
0x00 No dummy cycle
0x01 1 dummy cycle
0x02 2 dummy cycles
0x03 3 dummy cycles
0x04 4 dummy cycles
....
0x3E 62 dummy cycles
0x3F 63 dummy cycles
1 _{Refer to Data sheet of Memory vendors.}
Table 35-9. QSPI latency support
Memory Vendor
Winbond
Spansion
Macronix
Numonyx
Supported
Commands
None
0B, 3B, 6B, BB, EB
All
All
35.4.4.4 Serial Flash Address Register (QSPI_SFAR)
The Serial Flash Address Register contains the address for the next IP command. Bits 23 to 0 (bits 26 to 0
when MCR.EXT_ADD = 1) are used for the addressing of the flash device itself. Additional bits are used
to specify the access mode of the next IP command. Refer to Table 35-4 for the mapping between the
access mode and the QSPI_SFAR content and to Section 35.5.3, Normal Mode, for details about the
command triggering and command execution.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
35-13