PXD20RM Datasheet, PDF (165/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Address: Base + 0x00C8
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0
W
PDED[0:7]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-23. Power-down Exit Delay Register (PDEDR)
Table 5-19. Power-down Exit Delay Register (PDEDR) field descriptions
Field
0:23
24:31
Description
Reserved
Write of any value has no effect, read value is always 0.
PDED[0:7]: The delay between the power-down bit reset and the start of conversion
The power down delay is calculated as: PDED x 1/frequency of ADC clock
5.3.9 Data registers
5.3.9.1 Introduction
ADC conversion results are stored in data registers. There is one register per channel.
The 0 to 31 range shown below is the maximum range for the channel type. For the exact number of
available channels, please refer to Table 5-1.
CDR[32..63] = Extended internal channels
CDR[64..95] = External channels
Each data register also gives information regarding the corresponding result as described below.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
5-23