PXD20RM Datasheet, PDF (1408/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 41-3. Register Access Conventions (continued)
Convention
Description
rwm
A read/write bit that may be modified by hardware in some fashion other than by a reset.
w1c
Write one to clear. A flag bit that can be read, is cleared by writing a one, writing 0 has no effect.
Reset Value
0
Resets to zero.
1
Resets to one.
41.3.2.1 Motor Controller Control Register 0 (MCCTL0)
This register controls the operating mode of the SMC module.
Offset Module Base + 0x0000
0
1
2
3
4
5
6
R
0
W
MCPRE
0
0
0
DITH
Reset
0
0
0
0
0
0
0
Figure 41-2. Motor Controller Control Register 0 (MCCTL0)
.
Table 41-4. MCCTL0 Field Descriptions
7
MCTOIF
w1c
0
Field
MCPRE
DITH
MCTOIF
Description
Motor Controller Prescaler Select — MCPRE determines the prescaler value that sets the motor
controller timer counter clock frequency (f_TC). The clock source for the prescaler is the peripheral bus
clock (f_BUS) as shown in Figure 41-32. Writes to MCPRE will not affect the timer counter clock
frequency f_TC until the start of the next PWM period.
00 f_TC = f_Bus
01 f_TC = f_Bus/2
10 f_TC = f_Bus/4
11 f_TC = f_Bus/8
Motor Control/Driver Dither Feature Enable (refer to Section 41.4.1.3.5, Dither Bit
(MCCTL0[DITH]))
0 Dither feature is disabled.
1 Dither feature is enabled.
Motor Controller Timer Counter Overflow Interrupt Flag — This bit is set when a motor controller
timer counter overflow occurs. The bit is cleared by writing a 1 to the bit.
0 A motor controller timer counter overflow has not occurred since the last reset or since the bit was
cleared.
1 A motor controller timer counter overflow has occurred.
41-8
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor