PXD20RM Datasheet, PDF (155/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Address: Base + 0x002C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM}
W ^{95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80}
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM}
W ^{79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64}
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-9. Channel Interrupt Mask Register 2 (CIMR2)
Table 5-8. Channel Interrupt Mask Register (CIMR[1..2]) field descriptions
Field
31
n
Description
CIM0: Interrupt enable
When set (CIM0 = 1), interrupt for channel 0 is enabled.
CIMn: Interrupt enable
When set (CIMn = 1), interrupt for channel n is enabled.
5.3.3.5 Watchdog Threshold Interrupt Status Register (WTISR)
Address: Base + 0x0030
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
R0
W
Reset 0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
WDG WDG WDG WDG WDG WDG WDG WDG
3H 2H 1H 0H 3L 2L 1L 0L
w1c w1c w1c w1c w1c w1c w1c w1c
000000000000000
Figure 5-10. Watchdog Threshold Interrupt Status Register (WTISR)
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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