PXD20RM Datasheet, PDF (918/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

clock and the SCL period, it may be necessary to wait until the I²C is busy after writing the calling address
to the IBDR before proceeding with the following instructions. This is illustrated in the following example.
An example of the sequence of events which generates the START signal and transmits the first byte of
data (slave address) is shown below:
while (bit 5, IBSR ==1)// wait in loop for IBB flag to clear
bit4 and bit 5, IBCR = 1// set transmit and master mode, i.e. generate start condition
IBDR = calling_address// send the calling address to the data register
while (bit 5, IBSR ==0)// wait in loop for IBB flag to be set
25.6.1.3 Post-Transfer Software Response
Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte
communication is finished. The I²C Bus interrupt bit (IBIF) is set also; an interrupt will be generated if the
interrupt function is enabled during initialization by setting the IBIE bit. The IBIF (interrupt flag) can be
cleared by writing 1 (in the interrupt service routine, if interrupts are used).
The TCF bit will be cleared to indicate data transfer in progress by reading the IBDR data register in
receive mode or writing the IBDR in transmit mode. The TCF bit should not be used as a data transfer
complete flag as the flag timing is dependent on a number of factors including the I²C bus frequency. This
bit may not conclusively provide an indication of a transfer complete situation. It is recommended that
transfer complete situations are detected using the IBIF flag.
Software may service the I²C I/O in the main program by monitoring the IBIF bit if the interrupt function
is disabled. Note that polling should monitor the IBIF bit rather than the TCF bit since their operation is
different when arbitration is lost.
Note that when a “Transfer Complete” interrupt occurs at the end of the address cycle, the master will
always be in transmit mode, i.e. the address is transmitted. If master receive mode is required, indicated
by R/W bit in IBDR, then the Tx/Rx bit should be toggled at this stage. If Master does not receive an ACK
from Slave, then transmission must be re-initiated or terminated.
During slave mode address cycles (IAAS=1) the SRW bit in the status register is read to determine the
direction of the subsequent transfer and the Tx/Rx bit is programmed accordingly. For slave mode data
cycles (IAAS=0, the SRW bit is not valid. The Tx/Rx bit in the control register should be read to determine
the direction of the current transfer.
The following is an example software sequence for 'master transmitter' in the interrupt routine.
clear bit 1, IBSR// Clear the IBIF flag
if (bit 5, IBCR ==0)
slave_mode()// run slave mode routine
if (bit 4, IBCR ==0))
receive_mode()// run receive_mode routine
if (bit 0, IBSR == 1)// if NO ACK
end();// end transmission
else
IBDR = data_to_transmit// transmit next byte of data
25-22
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor