PXD20RM Datasheet, PDF (1235/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

NOTE
Each flag of the QSPI_SFMFR register enabled as source for an interrupt
prevents the QuadSPI module from entering Stop Mode or Module Disable
Mode when this flag is set. Refer to Section 35.5.4, Power Saving Features,
for details.
35.4.4.15 RX Buffer Data Registers 0–31 (QSPI_RBDR0–QSPI_RBDR31)
The QSPI_RBDR registers provide access to the individual entries in the RX Buffer. Refer to Table 35-28
for the byte ordering scheme.
Address: QSPI_BASE + 0x200 (QSPI_RBDR0)
...
QSPI_BASE + 0x27C (QSPI_RBDR31)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
RXDATA[31:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RXDATA[15:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 35-16. RX Buffer Data Registers 0–31 (QSPI_RBDR0–QSPI_RBDR31)
Table 35-22. QSPI_RBDR field descriptions
Field
RXDATA
Description
RX Data. The RXDATA field contains the data associated with the related RX Buffer entry. Data
format and byte ordering is given in Section 35.5.3.4, Byte Ordering of Serial Flash Read Data.
QSPI_RBDR0 corresponds to the actual position of the read pointer within the RX Buffer. The number of
valid entries available depends on the number of valid buffer entries available in the RX Buffer.
Example 1, RX Buffer filled completely with 32 words: In this case the address range for valid read access
extends from QSPI_RBDR0 to QSPI_RBDR31.
Example 2, RX Buffer filled with 5 valid words: RX Buffer fill level QSPI_RBSR[RDBFL] is 5. In this
case an access to QSPI_RBDR4 provides the last valid entry.
Any access beyond the range of valid RX Buffer entries provides undefined results.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
35-25