PXD20RM Datasheet, PDF (792/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Base + 0x0024
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R _{BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF}
W ^{63M 62M 61M 60M 59M 58M 57M 56M 55M 54M 53M 52M 51M 50M 49M 48M}
RESET: ₀
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R _{BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF}
W ^{47M 46M 45M 44M 43M 42M 41M 40M 39M 38M 37M 36M 35M 34M 33M 32M}
RESET: ₀
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Figure 20-11. Interrupt Mask Register High (IMRH)
Table 20-14. IMRH field descriptions
Field
Description
BUF63M –
BUF32M
Buffer MB_i Mask
Each bit enables or disables the respective FlexCAN Message Buffer (MB32 to MB63) Interrupt.
1 = The corresponding buffer Interrupt is enabled
0 = The corresponding buffer Interrupt is disabled
Note: Setting or clearing a bit in the IMRH register can assert or negate an interrupt request, if the
corresponding IFRH bit is set.
20.4.4.10 Interrupt Mask Register Low (IMRL)
This register allows to enable or disable any number of a range of 32 Message Buffer Interrupts. It contains
one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an interrupt after
a successful transmission or reception (i.e., when the corresponding IFRL bit is set).
20-26
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor