PXD20RM Datasheet, PDF (825/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

NOTE
A reset value of 1* in Figure 21-5 indicates that the reset value of these
registers is determined by Flash values in the shadow block. An erased
shadow block causes the reset value to be 1.
The HBL register is shown in Figure 21-5 and Table 21-6.
Offset: FLASH_REGS_BASE + 0x0008
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R HBE 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
0
W
HLOCK
Reset 0
0
0
0
0
0
0
0
0
0 1* 1* 1* 1* 1* 1*
Figure 21-5. High Address Space Block Locking Register (HBL)
Table 21-6. HBL Field Descriptions
Field
Description
HBE
HLOCK[5:0]
High Address Lock Enable This bit is used to enable the Lock registers (HLOCK) to be set or cleared by
register writes. This bit is a status bit only, and may not be written or cleared, and the reset value is 0. The
method to set this bit is to provide a password, and if the password matches, the HBE bit is set to reflect the
status of enabled, and is enabled until a reset operation occurs. For HBE, the password 0xB2B2_2222 must
be written to the HBL register.
0 High Address Locks are disabled, and cannot be modified.
1 High Address Locks are enabled to be written.
High Address Space Block Lock. HLOCK has the same characteristics as LLOCK. Please see this description
for more information. The block numbering for High Address Space starts with HLOCK[0] and continues until
all blocks are accounted.
HLOCK is not writable unless HBE is high.
21.3.2.4 Secondary Low/Mid Address Space Block Locking Register (SLL)
The Secondary Low/Mid Address Block Locking Register (SLL) provides an alternative means to protect
blocks from being modified. This has the effect of creating a “tiered” locking scheme to enable different
flash users to provide different default locking on blocks. These bits, along with bits in the LLOCK (LML),
determine if the block is locked from program or erase. An “OR” of LML and SLL determine the final
lock status.
NOTE
A reset value of 1* in Figure 21-6 indicates that the reset value of these
registers is determined by Flash values in the shadow block. An erased
shadow block causes the reset value to be 1.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
21-13