PXD20RM Datasheet, PDF (1013/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 27-43. TCD settings (master node, TX mode)
TCD field
CITER[14:0]
BITER[14:0]
NBYTES[31:0]
SADDR[31:0]
SOFF[15:0]
SSIZE[2:0]
SLAST[31:0]
DADDR[31:0]
DOFF[15:0]
DSIZE[2:0]
DLAST_SGA[31:0]
INT_MAJ
D_REQ
START
Value
Description
1
Single iteration for the “major” loop
1
Single iteration for the “major” loop
[4 + 4] + 0/4/8 = N Data buffer is stuffed with dummy bytes if the length is
not word aligned.
LINCR2 + BIDR + BDRL + BDRM
RAM address
4
Word increment
2
Word transfer
–N
LINCR2 address
4
Word increment
2
Word transfer
–N
No scatter/gather processing
0/1
Interrupt disabled/enabled
1
Only on the last TCD of the chain.
0
No software request
27.11.2 Master node, RX mode
On a master node in RX mode, the DMA interface requires a single RX channel. Each TCD controls a
single frame, except for the extended frames (multiple TCDs). The memory map associated to the TCD
chain (RAM area and LINFlexD registers) is shown in Figure 27-45.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
27-57