PXD20RM Datasheet, PDF (1432/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

NOTE
Both equations are only valid if MCPER[PER] is not equal to 0. M = 1 for
left or right aligned mode, M = 2 for center aligned mode.
Table 41-22 shows examples of the SMC channel frequencies that can be generated based on different
peripheral bus clock frequencies and the prescaler value.
Table 41-22. SMC Channel Frequencies (Hz),
MCPER[PER] = 256, MCCTL0[DITH] = 0, MCCCx[MCAM] = 0x2, 0x1
Prescaler
1
1/2
1/4
1/8
16 MHz
62500
31250
15625
7813
Peripheral Bus Clock Frequency
10 MHz
39063
19531
9766
4883
8 MHz
31250
15625
7813
3906
5 MHz
19531
9766
4883
2441
4 MHz
15625
7813
3906
1953
NOTE
Due to the selectable slew rate control of the outputs, clipping may occur on
short output pulses.
41.4.4 Output Switching Delay
In order to prevent large peak current draw from the motor power supply, selectable delays can be used to
stagger the high logic level to low logic level transitions on the SMC outputs. The timing delay, t_d, is
determined by the MCCCx[CD] bits in the corresponding channel control register and is selectable
between 0, 1, 2, or 3 motor controller timer counter clock cycles.
NOTE
A PWM channel gets disabled at the next timer counter overflow without
notice of the switching delay.
41.4.5 Operation in SMC stop mode
All module clocks are stopped and the associated port pins are set to their inactive state, which is defined
by the state of the MCCTL1[RECIRC] bit. The SMC module registers stay the same as they were prior to
entering stop mode. Therefore, after exiting from stop mode, the associated port pins will resume to the
same functionality they had prior to entering stop mode.
41.4.6 Short-circuit detection
Each PWM pin is equipped with a short-circuit detection function. Hence, 24 instances (4 for each PWM
module) of the short-circuit detector exist.
41-32
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor