PXD20RM Datasheet, PDF (324/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

System clock
123456
SCK
Slave sample
Master sample
Master SOUT
Slave SOUT
CS
t_CSC
t_ASC
t_CSC = CS to SCK delay.
t_ASC = After SCK delay.
Figure 10-17. DSPI Modified Transfer Format (MTFE = 1, CPHA = 1, f_SCK = f_SYS / 4)
10.9.5.5 Continuous Selection Format
Some peripherals must be deselected between every transfer. Other peripherals must remain selected
between several sequential serial transfers. The continuous selection format provides the flexibility to
handle both cases. The continuous selection format is enabled for the SPI configuration by setting the
CONT bit in the SPI command.
When the CONT bit = 0, the DSPI drives the asserted chip select signals to their idle states in between
frames. The idle states of the chip select signals are selected by the PCSIS field in the DSPIx_MCR.
Figure 10-18 shows the timing diagram for two four-bit transfers with CPHA = 1 and CONT = 0.
SCK
(CPOL = 0)
SCK
(CPOL = 1)
Master SOUT
Master SIN
CSx
t_CSC
t_ASC
t_DT
t_CSC = CS to SCK delay.
t_CSC
t_ASC = After SCK delay.
t_DT = Delay after transfer (minimum CS negation time).
Figure 10-18. Example of Non-Continuous Format (CPHA = 1, CONT = 0)
10-38
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor